library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

entity myram is
	generic(
		AddrWidth	: integer := 11;
		DataWidth	: integer := 8
	);
	port (
		A     : in std_logic_vector(AddrWidth - 1 downto 0);
		DIN   : in std_logic_vector(DataWidth - 1 downto 0);
		DOUT  : out std_logic_vector(DataWidth - 1 downto 0);
		OUT_EN: in std_logic := '0';
		IN_EN : in std_logic := '0';
		CLK   : in std_logic := '1';
		CS    : in std_logic := '0'
	);
end entity;

architecture rtl of myram is
	type Memory_Image is array (natural range <>) of std_logic_vector(DataWidth - 1 downto 0);
	signal	RAM		: Memory_Image(0 to 2 ** AddrWidth - 1);
begin
	process (Clk)
	begin
		if Clk'event and Clk = '1' then
			if CS = '1' then 
				if IN_En = '1' then
					RAM(to_integer(unsigned(A))) <= DIn;
				end if;
			end if;
		end if;
	end process;
	
	DOUT <= RAM(to_integer(unsigned(A)));
end architecture;